[PATCH] ARM: dts: msm8974: Add definitions for QCE & cryptobam

Andy Gross andy.gross at linaro.org
Fri Sep 16 11:50:12 PDT 2016

On Fri, Sep 16, 2016 at 08:38:01PM +0300, Iaroslav Gridin wrote:
> On Thu, Sep 15, 2016 at 04:18:42PM -0500, Andy Gross wrote:
> > Actually, on thinking about this more, the bam block itself only requires the
> > single clock.  The peripheral it is attached to has to keep its sanity during
> > the duration of the transfer (crypto).  The crypto requires 3 clocks, one of
> > which is the same clk the bam requires.
> > 
> > You can access the BAM registers with the bam_clk only, correct?
> Not preparing bam_clk degrades QCE performance about 3x, though.

If the CE2_CLK is the only required clk, that makes it the "bam_clk".  I see the
crypto requires getting all three clocks: AXI (bus), AHB (iface), and CE2 (core)

If the crypto is active during DMA transfers, which it has to be, then the
performance shouldn't degrade due to the BAM not preparing the AHB.



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