Tearing down DMA transfer setup after DMA client has finished

[Mason]

On 25/11/2016 15:12, Måns Rullgård wrote:

> Mason writes:
> 
>> On 25/11/2016 12:57, Måns Rullgård wrote:
>>
>>> The same DMA unit is also used for SATA, which is an off the shelf
>>> Designware controller with an in-kernel driver.  This interrupt timing
>>> glitch can actually explain some intermittent errors I've observed with
>>> it.
>>
>> FWIW, newer chips embed an AHCI controller, with a dedicated
>> memory channel.
>>
>> FWIW2, the HW dev said memory channels are "almost free", and he
>> would have no problem giving each device their own private channel
>> read/write pair.
> 
> We still need to deal with the existing hardware.

Can you confirm that your MBUS driver, in its current form,
does not support memcpy-type transfers, which generate two
IRQs (one from send agent, one from receive agent)?

Do you plan to support that, or is it just too quirky?

Regards.