[PATCH v5 1/4] clk: rockchip: fix big.LITTLE cores alternate reparent failed

Sun Mar 27 14:26:52 PDT 2016

Am Samstag, 26. März 2016, 14:37:53 schrieb Xing Zheng:
> On the RK3399, the order of the core's parents are LPLL/BPLL/DPLL/GPLL,
> there is incorrect to select bit_0 and bit_1 as the main and alternate
> parents for LPLL/BPLL. They should be configurable.
> 
> Signed-off-by: Xing Zheng <zhengxing at rock-chips.com>

I've folded this fix into the original patch [0]


Thanks
Heiko


[0] https://git.kernel.org/cgit/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v4.7-clk/next&id=268aebaa2410152bf91ea1ede6b284ff8138822d