[PATCH] dma: sun4i: expose block size and wait cycle configuration to DMA users
vinod.koul at intel.com
Fri Mar 11 02:09:02 PST 2016
On Fri, Mar 11, 2016 at 10:45:52AM +0100, Boris Brezillon wrote:
> On Fri, 11 Mar 2016 11:56:07 +0530
> Vinod Koul <vinod.koul at intel.com> wrote:
> > On Wed, Mar 09, 2016 at 12:06:27PM +0100, Boris Brezillon wrote:
> > > On Tue, 8 Mar 2016 08:25:47 +0530
> > > Vinod Koul <vinod.koul at intel.com> wrote:
> > > >
> > > > Why does dmaengine need to wait? Can you explain that
> > >
> > > I don't have an answer for that one, but when I set WAIT_CYCLES to 1
> > > for the NAND use case it does not work. So I guess it is somehow
> > > related to how the DRQ line is controlled on the device side...
> > Is the WAIT cycle different for different usages or same for all
> > usages/channels?
> In Allwinner BSP they adapt it on a per slave device basis, but since
> DMA channels are dynamically allocated, you can't know in advance which
> physical channel will be attached to a specific device.
And we have the correct values availble in datasheet for all usages
> Another option I considered was adding a new cell to the sun4i DT
> binding to encode these WAIT_CYCLES and BLOCK_SIZE information. But I'm
> not sure adding that to the DT is a good idea (not to mention that it
> would break DT ABI again, and given the last discussions on this topic,
> I'm not sure it's a good idea :-/).
Yes i was veering towards DT as well. This is a new property so ABI rules
wont break as long as driver still works with old properties.
But this nees to be property for clients and not driver. Client can then
More information about the linux-arm-kernel