[PATCH 1/1] ARM: dts: imx6qdl.dtsi: add "arm, shared-override" for pl310

[Peter Chen]

>
>Am Montag, den 13.06.2016, 09:42 +0000 schrieb Peter Chen:
>>
>> >Am Samstag, den 11.06.2016, 19:57 +0800 schrieb Shawn Guo:
>> >> + Lucas
>> >>
>> >> On Tue, Jun 07, 2016 at 05:39:25PM +0800, Peter Chen wrote:
>> >> > The imx6 SMP system has the same DMA memory coherency issue [1]
>> >> > with
>> >> > pl310 L2 controller. With this shared override bit set, the
>> >> > customer reports the DMA coherency issue is gone. Besides, I have
>> >> > tested the performance using USB ethernet with/without this bit,
>> >> > it shows no difference.
>> >> >
>> >> > [1] http://patchwork.ozlabs.org/patch/469362/
>> >> >
>> >> > Signed-off-by: Peter Chen <peter.chen at nxp.com>
>> >> > ---
>> >> >  arch/arm/boot/dts/imx6qdl.dtsi | 1 +
>> >> >  1 file changed, 1 insertion(+)
>> >> >
>> >> > diff --git a/arch/arm/boot/dts/imx6qdl.dtsi
>> >> > b/arch/arm/boot/dts/imx6qdl.dtsi index ed613eb..30e21ee 100644
>> >> > --- a/arch/arm/boot/dts/imx6qdl.dtsi
>> >> > +++ b/arch/arm/boot/dts/imx6qdl.dtsi
>> >> > @@ -185,6 +185,7 @@
>> >> >  			cache-level = <2>;
>> >> >  			arm,tag-latency = <4 2 3>;
>> >> >  			arm,data-latency = <4 2 3>;
>> >> > +			arm,shared-override;
>> >>
>> >> Lucas had an objection to the change [1], considering the case that
>> >> kernel is booted as non-secure.
>> >
>> >My objection to this change still stands. Configuring the L2C to be
>> >compliant to the
>> >ARMv7 ARM is at the same level as the CPU workarounds that can not be
>> >applied in secure mode. Those must be done in the firmware, if your
>> >firmware doesn't do it it's plain broken.
>> >
>>
>> Sorry, I not understand what's your mean. We only changes L2
>> configuration when the cache is disabled, what problem will be?
>>
>If the kernel is booted in non-secure mode, the L2 cache configuration register is RO
>and the kernel will crash on the attempt to write into this register.
>

Does that mean current mainline kernel for imx6qdl can't boot with non-secure mode, I see other
L2 configurations have been changed like "arm, tag-latency" and "arm,data-latency"? Did you try it?

Peter