[PATCH 07/13] ARM: dts: r8a7792: initial SoC device tree
kuninori.morimoto.gx at renesas.com
Mon Jun 13 18:08:48 PDT 2016
> Right, I had forgotten about that.
> Fortunately the clk-rcar-gen2 driver has a sane failure mode for this case ;-)
> it seems the RCAN clock can just be modeled as a fixed clock. However,
> its divider value isn't clear to me, as 15.9 MHz cannot be generated from PLL1
> using an integer divider. Morimoto-san, can you please ask for clarification?
Now, I asked to HW team about that.
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