[PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

[Jean-Francois Moine]

On Fri, 29 Jul 2016 21:17:30 +0200
Maxime Ripard <maxime.ripard at free-electrons.com> wrote:

> > > What happens if you actually want to set it to 100MHz?
> > 
> > There is no SDXC_CLK_100M in the mainline driver, and 100MHz is asked
> > only for 8 bits DDR at 50MHz.
> 
> You're missing the point.
> 
> clk_set_rate is supposed to apply a rate as close as possible as
> requested, there's no reason why you would request a rate twice as
> high as need.
> 
> You want to switch the clock from one mode to another, fine, create a
> new function for that. But don't hack an existing one.

I will not change the core clock stuff for this marginal case.
Flagging the clock as 'new mode capable' is enough.
Anyway, setting the 'new mode' bit to the clock divides the rate by
two, so, there is no reason to not use it.

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