[PATCH v3 2/2] clk: sunxi: Refactor A31 PLL6 so that it can be reused

[Chen-Yu Tsai]

On Sun, Jan 31, 2016 at 1:57 AM, Jean-Francois Moine <moinejf at free.fr> wrote:
> On Thu, 28 Jan 2016 20:22:38 +0100
> Maxime Ripard <maxime.ripard at free-electrons.com> wrote:
>
>> Remove the fixed dividers from the PLL6 driver to be able to have a
>> reusable driver that can be used across several SoCs that share the same
>> controller, but don't have the same set of dividers for this clock, and to
>> also be reused multiple times in the same SoC, since we're droping the
>> clock name.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
>> ---
>> Changes from v2
>>   - Rebased and converted over to the new factors refactoring. Fixed the
>>     retrieved rate
>>
>>  arch/arm/boot/dts/sun6i-a31.dtsi     | 36 ++++++++++++++++++------------------
>>  arch/arm/boot/dts/sun8i-a23-a33.dtsi | 25 +++++++++++++++++--------
>>  arch/arm/boot/dts/sun8i-a23.dtsi     |  2 +-
>>  arch/arm/boot/dts/sun8i-a33.dtsi     |  4 ++--
>>  arch/arm/boot/dts/sun8i-h3.dtsi      | 36 ++++++++++++++++++------------------
>>  drivers/clk/sunxi/clk-sunxi.c        | 32 ++++++++++++++++----------------
>>  6 files changed, 72 insertions(+), 63 deletions(-)
>
> Hi Maxime,
>
> Do you know that the DT definitions cannot be changed when they are in
> the mainline kernel?

This rule varies depending on who you talk to. :)

> Also, for the H3 PLL periph1 (aka PLL8), why didn't you create a
> 'pll8x2' clock with 'pll8' as a divider?

If it's used, it can be added later. No need to bloat the DT.


ChenYu