[PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze
michal.simek at xilinx.com
Tue Jan 26 07:21:35 PST 2016
On 26.1.2016 13:11, Arnd Bergmann wrote:
> On Tuesday 26 January 2016 10:59:12 Michal Simek wrote:
>>>> diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
>>>> index 3e3757f..1981948 100644
>>>> --- a/drivers/pci/host/pcie-xilinx.c
>>>> +++ b/drivers/pci/host/pcie-xilinx.c
>>>> @@ -92,7 +92,12 @@
>>>> #define ECAM_DEV_NUM_SHIFT 12
>>>> /* Number of MSI IRQs */
>>>> -#define XILINX_NUM_MSI_IRQS 128
>>>> +#define XILINX_NUM_MSI_IRQS 128
>>>> +#ifdef CONFIG_ARM
>>>> +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS
>>>> +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS)
>>> Something looks wrong here in the microblaze variant. What does NR_IRQS
>>> have to do with it?
>> Arnd: What was the story regarding NR_IRQS?
>> I remember some discussion about it but just forget.
>> Default value in include/asm-generic/irq.h is 64.
>> Current value is 32 because microblaze primary interrupt controller is
>> axi_intc core which has up to 32 input lines.
> The value in asm-generic is completely arbitrary, it's just something
> that happens to work for a number of the simpler architectures.
> Traditionally, there is a a fixed NR_IRQS which defines the maximum
> number of interrupts that can be used, and each irqchip has a fixed
> start offset below that number.
> On modern systems, you have CONFIG_SPARSE_IRQ, which lets an irqchip
> allocate its own interrupts, without an upper limit. This is more
> flexible and avoids preallocating space for all irq_desc instances,
> so it saves memory.
ok. That was the story. I will look if there is any issue to enable
SPARSE_IRQ for Microblaze.
I also need to move intc driver out of arch.
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