[PATCH] ARM: imx: Do L2 errata only if the L2 cache isn't enabled

[Russell King - ARM Linux]

On Fri, Feb 12, 2016 at 08:11:33AM +0100, Dirk Behme wrote:
> All the generic L2 cache handling code is encapsulated by a
> check if the L2 cache is enabled. If it's enabled already, the code
> is skipped.
> 
> For the i.MX6 specific L2 cache handling we missed this check.
> Add it.

What's the reasoning behind this?  The prefetch register is writable
while the L2 cache is enabled, unlike the auxiliary control register.

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