[PATCH v4] clk: sunxi: Refactor A31 PLL6 so that it can be reused

[Maxime Ripard]

Hi,

On Wed, Feb 10, 2016 at 06:04:20PM +0100, Jean-Francois Moine wrote:
> On Wed, 10 Feb 2016 13:53:33 +0100
> Maxime Ripard <maxime.ripard at free-electrons.com> wrote:
> 
> > > I don't agree:
> > > - you changed the DTs of many SoCs without any valid reason,
> > 
> > I did give you a significant number of reasons [1]. The fact that you
> > chose to ignore them is up to you.
> 
> Sorry, I don't see any reason for changing the DT definition of the pll6.
> The clock is named "pll6" with "#clock-cells = <1>;" in all DTs,
> and it works as it is.
> If you want an other clock as "pll8", with the same HW description,
> you must add new code for this clock.

That's not how it works. If an hardware block is strictly identical,
then it should use the same compatible.

The PLL8 is exactly the same one than PLL6, therefore it should use
the same compatible.

> > Except that it doesn't match the hardware and that the parenthood
> > relationship is inversed. The pll6 output is 24 MHz * n * k / 2, as
> > seen in any datasheet that uses it. Your clock driver doesn't
> > represent that fact.
> 
> The datasheet says that the pll6x2 output is 24 MHz * n * k, then, if
> I remember correctly my lessons at primary school, defining pll6 as
> (pll6x2 / 2) gives 24 MHz * n * k / 2 as the pll6 output. No?

Or, you could keep the same parenting relationship that we had and use
a simpler model. Ever heard of Occam's razor (and quite literally for
once)?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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