[PATCH] clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk

[Stephen Boyd]

On 12/01, Boris Brezillon wrote:
> bcm2835_pll_divider_off() is resetting the divider field in the A2W reg
> to zero when disabling the clock.
> 
> Make sure we preserve this value by reading the previous a2w_reg value
> first and ORing the result with A2W_PLL_CHANNEL_DISABLE.
> 
> Signed-off-by: Boris Brezillon <boris.brezillon at free-electrons.com>
> Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
> Cc: <stable at vger.kernel.org>
> ---

Applied to clk-next

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