IMX6S MRII does not work

Andy Ng andreas2025 at gmail.com
Wed Dec 7 14:11:38 PST 2016


I have hacked the file clk-imx6q.c and it works.

    /*Set enet_ref clock to 125M to supply for RGMII tx_clk */
    /*clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], 125000000);  */
    clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], 50000000);

On Wed, Dec 7, 2016 at 9:39 PM, Andy Ng <andreas2025 at gmail.com> wrote:
> Just an update...
>
> I have put a scope on ENET_REF_CLK to check what comes out from the
> PAD_GPIO16. The uboot shows 50MHz, and when in the kernel it goes
> 125MHz. And for sure that doesn't do
>
> On Wed, Dec 7, 2016 at 12:44 AM, Andy Ng <andreas2025 at gmail.com> wrote:
>> Hello,
>>
>> I have quite recent kernel linux-4.1.20 from Freescale's git repo.
>>
>>
>> I am using MRII and a fec setup that uses clock that goes to the phy too.
>>
>>
>> My dtsi has:
>>
>>     pinctrl_enet: enetgrp {
>>             fsl,pins = <
>>                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO        0x1b0b0
>>                 MX6QDL_PAD_ENET_MDC__ENET_MDC          0x1b0b0
>>                 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN  0x1b0b0
>>                 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0  0x1b0b0
>>                 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1  0x1b0b0
>>                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN      0x1b0b0
>>                 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER      0x1b0b0
>>                 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0    0x1b0b0
>>                 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
>>                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
>>
>>             >;
>>         };
>>
>>
>> the fec entry:
>>
>> &fec {
>>     pinctrl-names = "default";
>>     pinctrl-0 = <&pinctrl_enet>;
>>     phy-mode = "rmii";
>>     phy-reset-duration = <2>;
>>     phy-reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
>>     status = "okay";
>> };
>>
>>
>> The kernel comes up and detects the phy (MDIO works), but it seems fec
>> is not doing much:
>>
>> INIT: Entering runlevel: 5
>> Configuring network interfaces... RMII Detected
>> fec 2188000.ethernet eth0: Freescale FEC PHY driver [SMSC
>> LAN8710/LAN8720] (mii_bus:phy_addr=2188000.ethernet:00, irq=-1)
>> IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
>> udhcpc (v1.24.1) started
>> Sending discover...
>> Sending discover...
>> Sending discover...
>> No lease, forking to background
>> done.
>>
>> I have checked the code, and  I've found very few boards that use
>> rmii, and from those, most of them are using external clock for the
>> phy.
>>
>> I have the impression that GPIO_16_ENET_REF_CLK with SION bit ON may
>> not have been tested, as there is no imx6 ref board that uses
>> that mode.
>>
>> Did anyone else have seen the same issue?
>> Any thoughts will be very much appreciated.
>>
>> Thank you
>> Andy



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