[PATCH v3 02/12] mailbox: Add Tegra HSP driver

[Stephen Warren]

On 08/19/2016 11:32 AM, Thierry Reding wrote:
> From: Thierry Reding <treding at nvidia.com>
>
> This driver exposes a mailbox interface for interprocessor communication
> using the Hardware Synchronization Primitives (HSP) module's doorbell
> mechanism. There are multiple HSP instances and they provide additional
> features such as shared mailboxes, shared and arbitrated semaphores.
>
> A driver for a remote processor can use the mailbox client provided by
> the HSP driver and build an IPC protocol on top of this synchronization
> mechanism.

> +static int tegra_hsp_doorbell_startup(struct tegra_hsp_channel *channel)
...
> +	spin_lock_irqsave(&hsp->lock, flags);
> +
> +	value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
> +	value |= BIT(db->master);
> +	tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
> +
> +	spin_unlock_irqrestore(&hsp->lock, flags);
> +
> +	if (!tegra_hsp_doorbell_can_ring(db))
> +		return -ENODEV;

Should the error-check happen before enabling the RX path? Otherwise, 
presumably that HSP_DB_ENABLE bit should be cleared on failure.

> +static int tegra_hsp_probe(struct platform_device *pdev)

> +	dev_dbg(&pdev->dev, "regs: %pR (%p-%p)\n", res, hsp->regs, hsp->regs + resource_size(res) - 1);

Line width?