[RFC PATCH v3 1/7] irqchip: gic-v3: Reset BPR during initialization

[Marc Zyngier]

On 19/08/16 17:13, Daniel Thompson wrote:
> Currently, when running on FVP, CPU 0 boots up with its BPR changed from
> the reset value. This renders it impossible to (preemptively) prioritize
> interrupts on CPU 0.
> 
> This is harmless on normal systems since Linux typically does not
> support preemptive interrupts. It does however cause problems in
> systems with additional changes (such as patches for NMI simulation).
> 
> Many thanks to Andrew Thoelke for suggesting the BPR as having the
> potential to harm preemption.
> 
> Suggested-by: Andrew Thoelke <andrew.thoelke at arm.com>
> Signed-off-by: Daniel Thompson <daniel.thompson at linaro.org>

Acked-by: Marc Zyngier <marc.zyngier at arm.com>

	M.
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