[kernel-hardening] [PATCH 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching

[Catalin Marinas]

On Mon, Aug 15, 2016 at 12:43:31PM +0200, Ard Biesheuvel wrote:
> But, how about we store the reserved ASID in TTBR1_EL1 instead, and
> switch TCR_EL1.A1 and TCR_EL1.EPD0 in a single write? That way, we can
> switch ASIDs and disable table walks atomically (I hope), and we
> wouldn't need to change TTBR0_EL1 at all.

I did this before for AArch32 + LPAE (patches on the list sometime last
year I think). But the idea was nak'ed by the ARM architects. The
TCR_EL1.A1 can be cached somewhere in the TLB state machine, so you need
TLBI (IOW, toggling A1 does not guarantee an ASID switch).

-- 
Catalin