[PATCH v3 2/7] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
frank.wang at rock-chips.com
Fri Aug 5 01:34:42 PDT 2016
On 2016/8/5 3:10, Heiko Stübner wrote:
> Hi Xing,
> Am Dienstag, 2. August 2016, 15:19:56 schrieb Xing Zheng:
>> Export these source clocks for usbphy.
>> Signed-off-by: Xing Zheng <zhengxing at rock-chips.com>
> can you please provide a rationale why you need manual control over that
> intermediate clock?
Well, From below graph, you can see that 'clk_usbphyX_480m' is generated
from usb2phy, and 'clk_usbphy_480m' which select from
clk_usbphyX_480m_src via a gate (G13) provided 480M clock to other
| |__ clk_usbphy0_480m
| |__ ... ...
> The two usbphys seem to use the clk_usb2phyX_ref clocks, generate the 480m
> clocks, but do not seem to need the clk_usbphyX_480m_src gates.
Yeah, they used to be. However, the story went something like this,
Some PM suspend process related ehci/ohci controller are base on 480m
clocks, unfortunately, usb2-phy suspended earlier than ehci/ohci
(usb2-phy will be auto suspended if no devices plug-in), and the
clk-480m provided by it was disabled if no module used. As a result, the
PM suspend process was blocked when it run into ehci/ohci module.
Hence, we are planing to refer clk_usbphyX_480m_src into each ehci/ohci
driver. Maybe you will challenge why not refer clk_usbphy_480m directly?
because there are two ehci/ohci connected in the different usb2phy, and
only one clk_usbphy_480m clock was selected in clock tree.
> The clk_usbphyX_480m_src clocks on the other hand only lead to the
> clk_usbphy_480m mux, so I'd like some explanation on what you want to achieve
> here :-)
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