[PATCH v3 7/7] clk: rockchip: rk3399: Add support frac mode frequencies
zhengxing at rock-chips.com
Thu Aug 4 19:26:57 PDT 2016
On 2016年08月05日 03:19, Heiko Stübner wrote:
> Hi Xing,
> Am Dienstag, 2. August 2016, 15:22:59 schrieb Xing Zheng:
>> We need to support various display resolutions for external
>> display devices like HDMI/DP, the frac mode can help us to
>> acquire almost any frequencies, and need higher VCOs to reduce
>> clock jitters.
>> Signed-off-by: Xing Zheng<zhengxing at rock-chips.com>
> why does this need to be a separate rate array and cannot live in the general
> pll rate array?
> The plls are general purpose, so we shouldn't limit them arbitarily.
Yes, I understand your mean. :-)
> I currently only see some frequencies (594MHz, 297MHz, 54MHz) that are present
> in both arrays but have different settings. As your patch description says
> that these settings reduce clock jitter, wouldn't the general frequencies also
> profit from merging these new values into the general rate array?
and here are some of our ideas:
"WIth the frac mode and higher VCO to reduce clock jitters" that
suggestion is from IC designer.
There are many and various kinds resolution and needed frequencies for
external disaplay devices. For example, the DP needs:
... and so on
There some frequencies must be allocated with frac mode. We separate
these frequencies that are only used for display (VPLL) from the general
rate table, and put them to be classified into a frac mode table, we can
reduce the frequency of the query time, the two rate tables will not
interfere with each other. Because other PLLs don't need to assgin these
various frequencies with frac mode.
- Xing Zheng
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