[linux-sunxi] Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers
moinejf at free.fr
Mon Aug 1 06:52:46 PDT 2016
On Sat, 30 Jul 2016 12:19:03 +0200
Hans de Goede <hdegoede at redhat.com> wrote:
> Jean-Francois, can you submit a v2 of your patch and make the writing of
> SDXC_REG_NTSR depend on a new sun8i-a83t-mmc compatible ?
> Also you should probably drop the bits about the clock stuff from the
> commit message as that just seems to confuse people.
I submitted a new patch (sorry, I forgot the history), but it asks for
- in the old timings, the phase delays are set in the clock.
That's why there is a function clk_set_phase() which is called from
the MMC side.
- in the new timings, the delays are in the MMC register SDXC_REG_NTSR
In this case, the function clk_set_phase() is of no use
(also, by test, it seems that the phase delays set by hardware
reset do work, so, there is no need to set them), but,
- there is a bit in the clock telling that the new timings are used,
i.e. that the phase delays of the clock must be ignored.
Not setting this bit prevents the device to work (at least in the
A83T, the H3 seems more helpful).
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Jef | http://moinejf.free.fr/
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