[PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support

[Leo Li]

On Mon, Mar 7, 2016 at 3:50 AM, Marc Zyngier <marc.zyngier at arm.com> wrote:
> On Mon, 7 Mar 2016 11:36:22 +0800
> Minghuan Lian <Minghuan.Lian at nxp.com> wrote:
>
>> Some kind of NXP Layerscape SoC provides a MSI
>> implementation which uses two SCFG registers MSIIR and
>> MSIR to support 32 MSI interrupts for each PCIe controller.
>> The patch is to support it.
>>
>> Signed-off-by: Minghuan Lian <Minghuan.Lian at nxp.com>
>
> Acked-by: Marc Zyngier <marc.zyngier at arm.com>
>
> The DT binding still needs an Ack from the DT maintainers though (cc'd).

Marc,

Who will be responsible to pick this driver?  I see you are also one
of the maintainers for irqchip.  Can you pick up the driver?  The
binding has already gotten ACKed by the device tree maintainer.

Regards,
Leo