arm_coherent_dma_alloc

[Catalin Marinas]

On Tue, Sep 08, 2015 at 04:31:46AM +0000, Aggrwal Poonam wrote:
> > On Thu, Sep 03, 2015 at 04:50:56AM +0000, Aggrwal Poonam wrote:
> > > I am looking at the  file: "arch/arm/mm/dma-mapping.c"
> > >
> > > static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
> > >         dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) {
> > >         pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
> > >         void *memory;
> > >
> > >         if (dma_alloc_from_coherent(dev, size, handle, &memory))
> > >                 return memory;
> > >
> > >         return __dma_alloc(dev, size, handle, gfp, prot, true,
> > >                            __builtin_return_address(0)); }
> > >
> > > I want to understand the attributes of  memory allocated using
> > > __dma_alloc, in terms of cacheable.
> > 
> > If is_coherent == true (for __dma_alloc), the attributes are Normal
> > Cacheable (the case above).
> Thanks !.
> In this case; what are the values of  TEX[2:0], C, B bits?

Can you not read the code? Or at least run a kernel with some printks in
the right place?

TEX[0], C, B are 0b111 which means index 7 in the NMRR/PRRR registers
(or MAIR0/MAIR1 with LPAE).

-- 
Catalin