[PATCH] fpga: zynq-fpga: Fix unbalanced clock handling

[Moritz Fischer]

On Mon, Oct 19, 2015 at 1:22 PM, Moritz Fischer
<moritz.fischer at ettus.com> wrote:
> This commit fixes the unbalanced clock handling, where
> a failed probe would leave the clock with a prepare count of -1.

My English is broken, and it should've said enable count, will
resubmit ...  Sorry for the noise
>
> Reported-by: Josh Cartwright <joshc at ni.com>
> Signed-off-by: Moritz Fischer <moritz.fischer at ettus.com>
> ---
>  drivers/fpga/zynq-fpga.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
> index 103303c..617d382 100644
> --- a/drivers/fpga/zynq-fpga.c
> +++ b/drivers/fpga/zynq-fpga.c
> @@ -487,7 +487,7 @@ static int zynq_fpga_probe(struct platform_device *pdev)
>                                 &zynq_fpga_ops, priv);
>         if (err) {
>                 dev_err(dev, "unable to register FPGA manager");
> -               clk_disable_unprepare(priv->clk);
> +               clk_unprepare(priv->clk);
>                 return err;
>         }
>
> @@ -502,7 +502,7 @@ static int zynq_fpga_remove(struct platform_device *pdev)
>
>         priv = platform_get_drvdata(pdev);
>
> -       clk_disable_unprepare(priv->clk);
> +       clk_unprepare(priv->clk);
>
>         return 0;
>  }
> --
> 2.6.1
>

Moritz