l2c: Kernel panic in l2c310_enable() in non-secure mode

[Peter Maydell]

On 14 October 2015 at 18:45, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Wed, Oct 14, 2015 at 04:17:43PM +0200, Marc Gonzalez wrote:
>> Hello everyone,
>>
>> Internal error: Oops - undefined instruction: 0 [#1] PREEMPT SMP ARM
>>
>> On my platform, Linux v4.2 running in non-secure mode panics in
>> l2c310_enable() with the pc pointing at this instruction:
>>
>> c03390cc: ee013f30 mcr 15, 0, r3, cr1, cr0, {1}
>>
>> which corresponds to set_auxcr IIUC.
> ...
>> According to the Cortex A9 documentation,
>> ACTLR is RO in non-secure mode if NSACR[18]=0 and RW if NSACR[18]=1
>>
>> I suppose writing to a RO register cause the exception I see?
>
> It should not, the write should be ignored and no exception should be
> raised.

My reading of the v7 ARM ARM ('Read-only and write-only encodings'
under section B3.15.2) is that writes via MCR to a register defined as 'RO'
are UNPREDICTABLE. (In v8 this is tightened up, and such write
attempts are UNDEFINED.)

More specifically for this case, the Cortex-A9 TRM description of
NSACR.NS_SMP says that if it is zero then "A write to Auxiliary Control
Register in Non-secure state takes an Undefined Instruction exception".
So the behaviour Marc reports is expected if NS_SMP is 0.

thanks
-- PMM