l2c: Kernel panic in l2c310_enable() in non-secure mode

[Russell King - ARM Linux]

On Wed, Oct 14, 2015 at 04:47:59PM +0200, Marc Gonzalez wrote:
> Just to be sure, I changed set_auxcr() to a NOP. The kernel does not
> panic with that setup, and I can see the boot messages:
> 
> [    0.000000] l2x0_of_init: FOO
> [    0.000000] L2C-310 enabling early BRESP for Cortex-A9
> [    0.000000] L2C-310: enabling full line of zeros but not enabled in Cortex-A9
> [    0.000000] reg=0x104 val=0x66460801
> [    0.000000] reg=0x100 val=0x1
> [    0.000000] L2C-310 I prefetch enabled, offset 1 lines
> [    0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
> [    0.000000] L2C-310 cache controller enabled, 8 ways, 512 kB
> [    0.000000] L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x62460801
> 
> The "reg=0x%x val=0x%lx\n" lines are from tango_l2c_write_sec()
> 
> It seems the firmware forgot to enable FLOZ.

Wrong.  Do _not_ enable FLZ in the Cortex-A9.  FLZ needs the L2 cache
enabled _before_ the Cortex A9.  This is not something you can do in
firmware/boot loader/etc.  It has to be done by the kernel when the L2
cache is initialised.

If your firmware prevents this, sorry, you can't ever use FLZ.

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