[PATCH] clk: ti: omap5+: dpll: implement errata i810

Stephen Boyd sboyd at codeaurora.org
Mon Nov 30 11:35:38 PST 2015

On 11/30, Tero Kristo wrote:
> Errata i810 states that DPLL controller can get stuck while transitioning
> to a power saving state, while its M/N ratio is being re-programmed.
> As a workaround, before re-programming the M/N ratio, SW has to ensure
> the DPLL cannot start an idle state transition. SW can disable DPLL
> idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request
> active by setting a dependent clock domain in SW_WKUP.
> This errata impacts OMAP5 and DRA7 chips, so enable the errata for these.
> Signed-off-by: Tero Kristo <t-kristo at ti.com>
> ---

Acked-by: Stephen Boyd <sboyd at codeaurora.org>

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