[PATCH RFT] arm64: kasan: Make KASAN work with 16K pages + 48 bit VA

Catalin Marinas catalin.marinas at arm.com
Fri Nov 27 01:35:29 PST 2015


On Fri, Nov 27, 2015 at 11:12:28AM +0300, Andrey Ryabinin wrote:
> On 11/26/2015 07:40 PM, Ard Biesheuvel wrote:
> > On 26 November 2015 at 14:14, Andrey Ryabinin <aryabinin at virtuozzo.com> wrote:
> >> Currently kasan assumes that shadow memory covers one or more entire PGDs.
> >> That's not true for 16K pages + 48bit VA space, where PGDIR_SIZE is bigger
> >> than the whole shadow memory.
> >>
> >> This patch tries to fix that case.
> >> clear_page_tables() is a new replacement of clear_pgs(). Instead of always
> >> clearing pgds it clears top level page table entries that entirely belongs
> >> to shadow memory.
> >> In addition to 'tmp_pg_dir' we now have 'tmp_pud' which is used to store
> >> puds that now might be cleared by clear_page_tables.
> >>
> >> Reported-by: Suzuki K. Poulose <Suzuki.Poulose at arm.com>
> >> Signed-off-by: Andrey Ryabinin <aryabinin at virtuozzo.com>
> > 
> > I would argue that the Kasan code is complicated enough, and we should
> > avoid complicating it even further for a configuration that is highly
> > theoretical in nature.
> > 
> > In a 16k configuration, the 4th level only adds a single bit of VA
> > space (which is, as I understand it, exactly the issue you need to
> > address here since the top level page table has only 2 entries and
> > hence does not divide by 8 cleanly), which means you are better off
> > using 3 levels unless you *really* need more than 128 TB of VA space.
> > 
> > So can't we just live with the limitation, and keep the current code?
> 
> No objections from my side. Let's keep the current code.

Ard had a good point, so fine by me as well.

-- 
Catalin



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