[PATCH] ARM: zynq: Set bit 22 in PL310 AuxCtrl register (6395/1)

[Catalin Marinas]

On Tue, May 12, 2015 at 08:31:35AM +0200, Dirk Behme wrote:
> On 12.05.2015 08:22, Michal Simek wrote:
> >From: Thomas Betker <thomas.betker at rohde-schwarz.com>
> >
> >This patch is based on the
> >commit 1a8e41cd672f ("ARM: 6395/1: VExpress: Set bit 22 in the PL310
> >(cache controller) AuxCtlr register")
> 
> I've been under the impression that this shouldn't be done in the kernel,
> but in the boot loader/firmware:
> 
> https://lkml.org/lkml/2015/2/20/199
> 
> http://lists.denx.de/pipermail/u-boot/2015-March/207803.html

If you can fix it in the boot loader or firmware even better. If it's
not doable, this patch will help (if Russell takes it):

http://article.gmane.org/gmane.linux.ports.sh.devel/45685

-- 
Catalin