[PATCH v4 13/13] coresight-etm4x: Read only access to the tracer's ID registers

[Mathieu Poirier]

ETM ID registers contain valuable information about the capabilities
of the implementation and are very useful when configuring the device for
various trace scenarios.

Signed-off-by: Mathieu Poirier <mathieu.poirier at linaro.org>
---
 .../ABI/testing/sysfs-bus-coresight-devices-etm4x  | 90 ++++++++++++++++++++++
 drivers/hwtracing/coresight/coresight-etm4x.c      | 37 +++++++++
 2 files changed, 127 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
index bde788dfd3f7..2fe2e3dae487 100644
--- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
@@ -358,3 +358,93 @@ KernelVersion:	4.01
 Contact:	Mathieu Poirier <mathieu.poirier at linaro.org>
 Description:	(R) Print the content of the Peripheral ID3 Register
 		(0xFEC).  The value is taken directly from the HW.
+
+What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0
+Date:		April 2015
+KernelVersion:	4.01
+Contact:	Mathieu Poirier <mathieu.poirier at linaro.org>
+Description:	(R) Returns the tracing capabilities of the trace unit (0x1E0).
+		The value is taken directly from the HW.
+
+What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1
+Date:		April 2015
+KernelVersion:	4.01
+Contact:	Mathieu Poirier <mathieu.poirier at linaro.org>
+Description:	(R) Returns the tracing capabilities of the trace unit (0x1E4).
+		The value is taken directly from the HW.
+
+What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2
+Date:		April 2015
+KernelVersion:	4.01
+Contact:	Mathieu Poirier <mathieu.poirier at linaro.org>
+Description:	(R) Returns the maximum size of the data value, data address,
+		VMID, context ID and instuction address in the trace unit
+		(0x1E8).  The value is taken directly from the HW.
+
+What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3
+Date:		April 2015
+KernelVersion:	4.01
+Contact:	Mathieu Poirier <mathieu.poirier at linaro.org>
+Description:	(R) Returns the value associated with various resources
+		available to the trace unit.  See the Trace Macrocell
+		architecture specification for more details (0x1E8).
+		The value is taken directly from the HW.
+
+What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4
+Date:		April 2015
+KernelVersion:	4.01
+Contact:	Mathieu Poirier <mathieu.poirier at linaro.org>
+Description:	(R) Returns how many resources the trace unit supports (0x1F0).
+		The value is taken directly from the HW.
+
+What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5
+Date:		April 2015
+KernelVersion:	4.01
+Contact:	Mathieu Poirier <mathieu.poirier at linaro.org>
+Description:	(R) Returns how many resources the trace unit supports (0x1F4).
+		The value is taken directly from the HW.
+
+What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8
+Date:		April 2015
+KernelVersion:	4.01
+Contact:	Mathieu Poirier <mathieu.poirier at linaro.org>
+Description:	(R) Returns the maximum speculation depth of the instruction
+		trace stream. (0x180).  The value is taken directly from the HW.
+
+What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9
+Date:		April 2015
+KernelVersion:	4.01
+Contact:	Mathieu Poirier <mathieu.poirier at linaro.org>
+Description:	(R) Returns the number of P0 right-hand keys that the trace unit
+		can use (0x184).  The value is taken directly from the HW.
+
+What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10
+Date:		April 2015
+KernelVersion:	4.01
+Contact:	Mathieu Poirier <mathieu.poirier at linaro.org>
+Description:	(R) Returns the number of P1 right-hand keys that the trace unit
+		can use (0x188).  The value is taken directly from the HW.
+
+What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11
+Date:		April 2015
+KernelVersion:	4.01
+Contact:	Mathieu Poirier <mathieu.poirier at linaro.org>
+Description:	(R) Returns the number of special P1 right-hand keys that the
+		trace unit can use (0x18C).  The value is taken directly from
+		the HW.
+
+What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12
+Date:		April 2015
+KernelVersion:	4.01
+Contact:	Mathieu Poirier <mathieu.poirier at linaro.org>
+Description:	(R) Returns the number of conditional P1 right-hand keys that
+		the trace unit can use (0x190).  The value is taken directly
+		from the HW.
+
+What:		/sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13
+Date:		April 2015
+KernelVersion:	4.01
+Contact:	Mathieu Poirier <mathieu.poirier at linaro.org>
+Description:	(R) Returns the number of special conditional P1 right-hand keys
+		that the trace unit can use (0x194).  The value is taken
+		directly from the HW.
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 0568e4413411..f0b50af4fc30 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -2238,6 +2238,37 @@ static struct attribute *coresight_etmv4_mgmt_attrs[] = {
 	NULL,
 };
 
+coresight_simple_func(trcidr0, TRCIDR0);
+coresight_simple_func(trcidr1, TRCIDR1);
+coresight_simple_func(trcidr2, TRCIDR2);
+coresight_simple_func(trcidr3, TRCIDR3);
+coresight_simple_func(trcidr4, TRCIDR4);
+coresight_simple_func(trcidr5, TRCIDR5);
+/* trcidr[6,7] are reserved */
+coresight_simple_func(trcidr8, TRCIDR8);
+coresight_simple_func(trcidr9, TRCIDR9);
+coresight_simple_func(trcidr10, TRCIDR10);
+coresight_simple_func(trcidr11, TRCIDR11);
+coresight_simple_func(trcidr12, TRCIDR12);
+coresight_simple_func(trcidr13, TRCIDR13);
+
+static struct attribute *coresight_etmv4_trcidr_attrs[] = {
+	&dev_attr_trcidr0.attr,
+	&dev_attr_trcidr1.attr,
+	&dev_attr_trcidr2.attr,
+	&dev_attr_trcidr3.attr,
+	&dev_attr_trcidr4.attr,
+	&dev_attr_trcidr5.attr,
+	/* trcidr[6,7] are reserved */
+	&dev_attr_trcidr8.attr,
+	&dev_attr_trcidr9.attr,
+	&dev_attr_trcidr10.attr,
+	&dev_attr_trcidr11.attr,
+	&dev_attr_trcidr12.attr,
+	&dev_attr_trcidr13.attr,
+	NULL,
+};
+
 static const struct attribute_group coresight_etmv4_group = {
 	.attrs = coresight_etmv4_attrs,
 };
@@ -2247,9 +2278,15 @@ static const struct attribute_group coresight_etmv4_mgmt_group = {
 	.name = "mgmt",
 };
 
+static const struct attribute_group coresight_etmv4_trcidr_group = {
+	.attrs = coresight_etmv4_trcidr_attrs,
+	.name = "trcidr",
+};
+
 static const struct attribute_group *coresight_etmv4_groups[] = {
 	&coresight_etmv4_group,
 	&coresight_etmv4_mgmt_group,
+	&coresight_etmv4_trcidr_group,
 	NULL,
 };
 
-- 
1.9.1