[PATCH] ARM: zynq: Set bit 22 in PL310 AuxCtrl register (6395/1)
joshc at ni.com
Tue May 12 08:12:05 PDT 2015
Something tells me that Russell's patch system won't like to accept a
patch with a duplicate ID (although, I could be wrong).
On Tue, May 12, 2015 at 08:22:01AM +0200, Michal Simek wrote:
> From: Thomas Betker <thomas.betker at rohde-schwarz.com>
> This patch is based on the
> commit 1a8e41cd672f ("ARM: 6395/1: VExpress: Set bit 22 in the PL310
> (cache controller) AuxCtlr register")
> Clearing bit 22 in the PL310 Auxiliary Control register (shared
> attribute override enable) has the side effect of transforming Normal
> Shared Non-cacheable reads into Cacheable no-allocate reads.
> Coherent DMA buffers in Linux always have a cacheable alias via the
> kernel linear mapping and the processor can speculatively load cache
> lines into the PL310 controller. With bit 22 cleared, Non-cacheable
> reads would unexpectedly hit such cache lines leading to buffer
> For Zynq, this fix avoids memory inconsistencies between Gigabit
> Ethernet controller (GEM) and CPU when DMA_CMA is disabled.
In practice, we've seen corruption not only with the GEM but also the
UDC (and likely other things as well). So, this patch is welcome!
> Suggested-by: Punnaiah Choudary Kalluri <punnaia at xilinx.com>
> Signed-off-by: Thomas Betker <thomas.betker at rohde-schwarz.com>
> Signed-off-by: Michal Simek <michal.simek at xilinx.com>
This feels like stable material as well, to me. (Although, I'd expect a
bit of manual work to get it backported, with the fairly recent L2
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