[PATCH v7 3/5] Documentation: Add documentation for the APM X-Gene SoC EDAC DTS binding

Rob Herring robherring2 at gmail.com
Mon May 4 15:36:19 PDT 2015

On Fri, May 1, 2015 at 2:59 PM, Loc Ho <lho at apm.com> wrote:
> Hi Rob,
>>>>> I think we should first agreed on the DT binding and let's not worry
>>>>> about APEI. Then, whether we have one file or multiple file. Again,
>>>>> the HW consist of:
>>>>> 1. One top level interrupt and status registers
>> For these registers, are there ECC specific functions here or just
>> normal interrupt control/status bits (mask/unmask/status)? Assuming
>> the later, then you should make this block an interrupt-controller.
>> Then this is the interrupt-parent for the rest of the blocks.
> This is the only item remain before I generate an patch with just the
> memory controller. Most of the code that I see are actually an
> interrupt controller HW. As it is just an interrupt mask and status
> registers, is there an example in Linux that I can model after? Also,
> I am not quite convince as to why we can't just share the interrupt
> and request it by each memory controller?

Pretty much anything that calls irq_set_chained_handler. If you don't
need to touch the shared registers and can set them up once at boot
time, then you could just do shared irq handlers. But if you have to
clear the interrupt within the PCP, you need a demuxer.


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