some question about Set bit 22 in the PL310 (cache controller) AuxCtlr register

[Russell King - ARM Linux]

On Tue, Mar 10, 2015 at 04:31:34PM +0000, Catalin Marinas wrote:
> It's not entirely safe either. I guess the assumption is that CMA
> allocates from highmem which is not mapped in the kernel linear mapping.
> However, to be able to flush the caches for such highmem pages, they
> need to be mapped (kmap_atomic() in __dma_clear_buffer()) but there is a
> small window between dmac_flush_range() and kunmap_atomic() where
> speculative cache line fills can still happen.

That really ought to be fixed.

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