[Question] How can we support outer shareable on ARM64?

leizhen thunder.leizhen at huawei.com
Mon Mar 2 18:32:02 PST 2015

On 2015/3/2 18:44, Catalin Marinas wrote:
> On Mon, Mar 02, 2015 at 04:02:12PM +0800, leizhen wrote:
>> Now, both cacheable memory shareability attribute and barrier are
>> fixed to inner shareable.
> That's correct for memory attributes. As for barriers, the mb()
> generates full system DSB.
>> But I afraid some hardware need outer shareable.
> Why? All processors or devices controlled by an operating system are
> expected to be in the same inner shareable domain (see shareable memory
> in B2.8.1 in the ARMv8 ARM).
OK. Thank you for help. I saw that sentence:
This architecture assumes that all PEs that use the same operating system or hypervisor are in the same Inner
Shareable shareability domain.

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