[PATCH v7] dma: Add Xilinx AXI Direct Memory Access Engine driver support

Nicolae Rosia nicolae.rosia at gmail.com
Sat Jun 27 07:44:38 PDT 2015

On Sat, Jun 27, 2015 at 5:40 PM, Vinod Koul <vinod.koul at intel.com> wrote:
>> Please let me know if you are not clear.
> No sorry am not...
> I asked how the device address in configured. For both MM2S S2MM you are
> using sg for memory address, where are you getting device adress, are you
> assuming/hardcoding or getting somehow, if so how?
As the name says, one end is memory (MM) and the other end is an AXI4
Stream Bus (S) which has no concept of memory address.
So yes, it is hardcoded at design time.

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