[PATCH v2 2/3] IRQ/Gic-V3: Change arm-gic-its to support the Mbigen interrupt
marc.zyngier at arm.com
Fri Jun 26 01:45:01 PDT 2015
On 23/06/15 10:29, Thomas Gleixner wrote:
> On Tue, 23 Jun 2015, majun (F) wrote:
>> 在 2015/6/19 7:52, Thomas Gleixner 写道:
>>> On Mon, 15 Jun 2015, majun (F) wrote:
>>>> 在 2015/6/12 18:48, Thomas Gleixner 写道:
>>>>> Can you please provide a proper description of this mbigen chip and
>>>>> explain WHY you think that it needs all this special hackery?
>>> You carefully avoided to provide a proper description of this mbigen
>>> chip and how it needs to be integrated into the GIC/ITS whatever
>> Mbigen means Message Based Interrupt Generator.
>> Its a kind of interrupt controller collects
>> the interrupts from external devices and generate msi interrupt.
>> Mbigen is applied to reduce the number of wire connected interrupts.
>> As the peripherals increasing, the interrupts lines needed is increasing
>> much, especially on the Arm64 server soc.
>> Therefore, the interrupt pin in gic is not enought for so many perpherals.
>> Mbigen is designed to fix this problem.
>> Mbigen chip locates in ITS or outside of ITS.
>> The working flow of Mbigen shows as below:
>> external devices ------> MBIGEN ------->ITS
>> The devices connect to Mbigen chip through wire connecting way.
>> Mbigen detects and collectes the interrupts from the these devices.
>> Then, Mbigen generats the MBI interrupts by writting the ITS
>> Translator register.
> So it's nothing else than a non PCI based MSI implementation which
> means it can simply use the generic MSI infrastructure and implement a
> interrupt domain/chip which implements the MBI specific parts and has
> the ITS as its parent domain.
> No hackery in ITS and no extra functionality in the core irq code. It
> just can use the existing infrastructure. The only extra you need is a
> proper way to retrieve the pointer to the ITS domain. Everything else
> just falls in place.
I may have a proposal for that. Stay tuned.
Jazz is not dead. It just smells funny...
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