[PATCH v2 0/7] clk: sunxi: Add support for the Audio PLL

Maxime Ripard maxime.ripard at free-electrons.com
Thu Jun 4 06:27:52 PDT 2015

Hi Mike, Stephen,

On Thu, May 21, 2015 at 10:53:59PM +0200, Maxime Ripard wrote:
> Hi,
> This serie adds support for the PLL2 aka the Audio PLL on the
> Allwinner A10 and the later SoCs.
> This is the first stepping stone to get the audio support merged.
> This serie is built on top of a generic clk-factor driver to handle
> clock that multiply their parent clock rate (mostly PLL's), in order
> to provide the driver for the PLL2 base clock, and then adds the
> drivers for the clock that derive from the Audio PLL.
> Thanks!
> Maxime

Any comments on that (especially the first patch)?


Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
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