[PATCH v7 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR

Mitchel Humpherys mitchelh at codeaurora.org
Tue Jan 20 11:45:55 PST 2015

On Tue, Jan 20 2015 at 06:16:43 AM, Will Deacon <will.deacon at arm.com> wrote:
> Hey Mitch,
> On Wed, Oct 29, 2014 at 09:13:40PM +0000, Mitchel Humpherys wrote:
>> Currently, we provide the iommu_ops.iova_to_phys service by doing a
>> table walk in software to translate IO virtual addresses to physical
>> addresses. On SMMUs that support it, it can be useful to ask the SMMU
>> itself to do the translation. This can be used to warm the TLBs for an
>> SMMU. It can also be useful for testing and hardware validation.
>> Since the address translation registers are optional on SMMUv2, only
>> enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1
>> and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec.
>> Signed-off-by: Mitchel Humpherys <mitchelh at codeaurora.org>
>> ---
>> Changes since v6:
>>   - added missing lock
>>   - fixed physical address mask
> I had a go at rebasing this onto my current queue, but ended up making
> quite a few changes. Can you take a look at the result, please?
> Patch below (also on my for-joerg/arm-smmu/updates branch).

The modified patch looks good to me.  Thanks!


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