[PATCH RESEND] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories

[Peter Rosin]

Nicolas Ferre wrote:
> Le 14/01/2015 14:20, Peter Rosin a écrit :
> > From: Peter Rosin <peda at axentia.se>
> >
> > The DDRSDR controller (on the ATSAMA5D31) fails miserably to put
> > LPDDR1 memories in self-refresh. Force the controller to think it has
> > DDR2 memories during the self-refresh period, as the DDR2 self-refresh
> > spec is equivalent to LPDDR1, and is correctly implemented in the
> controller.
> >
> > Assume that the second controller has the same fault, and that other
> > CPUs in the family has the same problem, but that is untested.
> >
> > Signed-off-by: Peter Rosin <peda at axentia.se>
> 
> I've just verified your code and the scope of this issue and your
> implementation makes perfect sense.
> 
> Acked-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> 
> Peter,
> Thanks for your patch. You will probably see it appearing in 3.20 or 3.21.

Great!

> Wenyou,
> Can you please integrate the patch from Peter in your current rework of the
> PM routines (keeping his authorship of course)?
> Please tell me if I can help with this.

To be 100% honest with credits, I should perhaps have mentioned that I
received an unconditional proof-of-concept patch from Atmel support
(Case 00007347). I'm not certain who wrote that patch, but the only thing
that has survived is the idea to temporarily use DDR2 mode and the trivial
change of the register field width in the header file. So, I do not feel too
dishonest by claiming authorship...

Cheers,
Peter