[PATCH v6] i2c: cadence: Check for errata condition involving master receive

[Wolfram Sang]

On Wed, Jan 14, 2015 at 12:04:59AM +0530, Harini Katakam wrote:
> Cadence I2C controller has the following bugs:
> - completion indication is not given to the driver at the end of
> a read/receive transfer with HOLD bit set.
> - Invalid read transaction are generated on the bus when HW timeout
> condition occurs with HOLD bit set.
> 
> As a result of the above, if a set of messages to be transferred with
> repeated start includes any message following a read message,
> completion is never indicated and timeout occurs.
> Hence a check is implemented to return -EOPNOTSUPP for such sequences.
> 
> Signed-off-by: Harini Katakam <harinik at xilinx.com>
> Signed-off-by: Vishnu Motghare <vishnum at xilinx.com>

Applied to for-next with some whitespace corrections, thanks!

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