[PATCH 0/6] ARM: mvebu: mvebu-mbus and I/O coherency fixes

[Russell King - ARM Linux]

On Sat, Jan 10, 2015 at 08:57:21PM +0100, Thomas Petazzoni wrote:
> We will indeed need to do more extensive testing and review. However, I
> don't agree that this should prevent this patch from going to stable:
> the current situation in the kernel (and also past kernels) is known to
> be broken: DMA coherent mappings allocated by dma_alloc_coherent() are
> *not* coherent in the current situation. Writes made by the device to
> the memory are not guaranteed to be immediately visible to the CPU,
> unless an explicit I/O sync barrier is done, which obviously is never
> done for DMA coherent mappings since those are assumed by Linux to be
> coherent, and therefore not require any cache maintenance operation.

That's actually an incorrect statement.

On all ARMv6+ where DMA coherent memory is "normal memory, non-cached,
write combine" but because it's "normal memory", memory barriers are
required.  This is why we have the memory barriers in readl() and
writel().

Remember, DMA coherent memory is about avoiding effects from caching,
not about avoiding weakly ordered memory effects.

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