[PATCH] iommu/arm-smmu: don't touch the secure STLBIALL register

[Rob Herring]

On Tue, Jan 6, 2015 at 2:16 PM, Mitchel Humpherys
<mitchelh at codeaurora.org> wrote:
> On Tue, Jan 06 2015 at 06:15:07 AM, Will Deacon <will.deacon at arm.com> wrote:
>>>      /* Invalidate the TLB, just in case */
>>> -    writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
>>>      writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
>>>      writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
>>
>> I was slightly worried that this would break the Calxeda implementation
>> with ARM_SMMU_OPT_SECURE_CFG_ACCESS, but actually these registers aren't
>> even aliased there so I think there's a bigger bug for them.
>>
>> Anyway, given that their hardware has gone the way of the dodo, I'll take
>> the patch as-is unless you have any further comments?
>>
>> Will
>
> Yeah I agree that this shouldn't affect the (now defunct) Calxeda
> implementation.  I've tested this on some hardware here and we crash
> when we touch that register since it's secure-only (not banked, as you
> mentioned).

It's not quite dead:

http://www.eweek.com/servers/calxedas-arm-based-server-chips-re-emerge-with-new-company.html

But AFAIK, production systems don't enable the SMMU, but someone could
still want to at some point. A note in the commit log here would be
nice so it gets recorded.

Rob