[PATCH] arm64: dts: Fix GIC reg sizes for APM X-Gene

[Christoffer Dall]

On Sat, Feb 21, 2015 at 03:56:17PM -0600, Rob Herring wrote:
> On Thu, Feb 19, 2015 at 1:03 PM, Christoffer Dall
> <christoffer.dall at linaro.org> wrote:
> > On Thu, Feb 19, 2015 at 12:23:15PM -0600, Rob Herring wrote:
> >> On Tue, Jan 27, 2015 at 1:03 AM, Pranavkumar Sawargaonkar
> >> <psawargaonkar at apm.com> wrote:
> >> > In APM X-Gene, GIC register space is 64K aligned while the sizes mentioned
> >> > in the dt are 4K aligned. This breaks KVM when kernel is built with 64K page
> >> > size due to size alignment checking in vgic driver for VCPU Control and
> >> > VCPU register.
> >> >
> >> > This patch corrects the sizes to be inline with the hardware spec.
> >>
> >> This does not make sense. The GIC regions are still only 4 or 8KB and
> >> the h/w description should reflect that. For implementations using
> >> gic-400 and the addressing decode trick, the rest of the register
> >> range is also not safe to access given it is multiple mapped. Also,
> >> this wastes virtual space, but I guess we don't care on 64-bit.
> >>
> >> KVM should be fixed to only check base address alignment. Size
> >> alignment does not matter (if it does, then you need to fix all
> >> register blocks).
> >>
> > It matters if you want to ensure that the 64K page you are assigning to
> > a guest for the GIC virtual CPU interface contains only GIC virtual CPU
> > mappings, and not other random stuff that the guest is not allowed to
> > touch.
> 
> Good point.
> 
> > How else should this be enforced?
> 
> Rely on correct h/w design? You'll have to repeat this every time you
> want to do pass-thru of a device.
> 
> What do you do if 64K mapping is not supported? Fallback to emulation
> of the CPU interface?

Agree with Peter on these two points.

> 
> Are there other DTSs that need to be fixed?
> 
Not sure really, AMD Seattle works with 64K pages IIRC.

Thanks,
-Christoffer