imx6 GPIO1 interrupts
stillcompiling at gmail.com
Thu Feb 19 10:09:40 PST 2015
Freescale imx6 has gpios use shared irqs that trigger across 16 pins
at a time. These are supported in the mainline kernel.
The first 8 pins on GPIO1 also have their own interrupts on the GIC.
I have a kluge sort of working, and am wondering what it would take
for me to fully support these in a way that might be mainlined.
What I am doing:
(error checking removed for brevity)
/* request the shared gpio irq to set the correct edge bits */
gpiod = gpiod_get(my->dev, "diffirq");
ret = gpiod_direction_input(gpiod);
fake_irq = gpiod_to_irq(gpiod);
ret = request_irq(fake_irq, no_action, 0, "gpio irq", mydev);
/* Use the ARM GPIO4 irq */
mydev->irq = irq_of_parse_and_map(mydev->dev->of_node, 0);
ret = request_irq(mydev->irq, my_irq_handler, 0, "my fpga", mydev);
This seems to work, but both irq appear in /proc/interrupts, and if I
try to change the affinity of the hard irq the gpio irq gets all the
traffic (or something)
Looking at the code in drivers/gpio/gpio-mxc.c, it seems like almost
all the code for full hardware irq support is already there, but just
out of reach to my brain. I think I just need the hardware irq to call
gpio_set_irq_type() for its set_type function.
What is the proper way to do this? Do I need another virtual irq_chip
for the 8 gpio1 irqs? Can something like that be set up in the gpio
probe, or do I need to catch it earlier when the GIC is being
...or am I way off base here?
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