[BUG] ARM: socfpga: L2 cache init

[Russell King - ARM Linux]

On Tue, Feb 17, 2015 at 04:00:47PM -0600, Dinh Nguyen wrote:
> On Fri, Feb 13, 2015 at 2:01 AM, Steffen Trumtrar
> <s.trumtrar at pengutronix.de> wrote:
> > Yes, seems very likely that Russell is right.
> 
> The bug doesn't happen if I disable the L2. Digging more...

What ensures that the value written to socfpga_cpu1start_addr (by
of_property_read_u32() in socfpga_sysmgr_init(), called at .init_irq
time) is visible to the secondary CPU?

>From what I can see, the physical address written there is not
guaranteed to be flushed from all levels of cache.

The flush_cache_all() in socfpga_boot_secondary() won't do the job -
that won't touch the L2C-310.

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