[PATCH 0/4] arm: Privileged no-access for LPAE

[Catalin Marinas]

On Thu, Dec 10, 2015 at 11:40:44AM -0800, Kees Cook wrote:
> [thread necromancy]
> 
> This series looks good to me. I'd love to see it accepted. At the very
> least the cleanups look like no-brainers. :)
> 
> Please consider the series:
> 
> Reviewed-by: Kees Cook <keescook at chromium.org>
> 
> Thanks for working on it!

Thanks for the review. After some more (internal) discussions around
these patches, I need to get clarification on the architecture whether
changing the TTBCR.A1 bit is enough to guarantee an ASID change (I do
this trick to change to the reserved ASID and avoid TLB invalidation as
normally required by changes to translation control registers). If
that's not allowed by the architecture, I would have to change the
patches to switch to a reserved TTBR0 rather than disabling TTBR0 walks
at the TTBCR level.

-- 
Catalin