[PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

[Jean-Francois Moine]

On Tue, 8 Dec 2015 09:32:24 +0100
Maxime Ripard <maxime.ripard at free-electrons.com> wrote:

> If the H3 display block is done the same way than the A10 (and later)
> one on this aspect, then the TCON has two channels with two different
> streaming (or functional, you pick the name) clocks. The channel 0 is
> usually used for RGB, the channel 1 for HDMI, composite and VGA.
> 
> Maybe they just added different bus gates for those two different
> channels, and moved HDMI to the channel 0.
> 
> Anyway, that can always be changed later on if we have more clue on
> what's going on.

I don't know about the other Allwinner chips, and your DRM driver for
these ones cannot be reused for the H3 because its display engine
(DE.2) is completely different.

The DE2 runs at 432MHz and treats both LCDs. The TCON1 runs at a fixed
rate, 200MHz, and the streaming rates are defined by the HDMI (LCD0) and
TCON0 (LCD1) clocks.

BTW, I hope to submit a H3 DRM driver before new year.

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