Domain faults when CONFIG_CPU_SW_DOMAIN_PAN is enabled

[Russell King - ARM Linux]

On Thu, Dec 03, 2015 at 04:12:06PM +0000, Peter Rosin wrote:
> Since it seems like a race is at the bottom of the observed problems, I'm
> going to look for things that look racy. The things that stand out to me
> are:
> 
> * uaccess.h:modify_domain() does a read-modify-write on DACR using
>   get_domain and set_domain, and I don't see any locking. Is that
>   safe? Why?

It's safe:
* the DACR is per-CPU
* all exceptions preserve the original DACR value when they return.
  This is done by storing the DACR value at entry onto the stack, along
  with the register set, and restoring it along with the register set
  on exit from exception processing, as if "nothing ever happened".
  This includes if the exception processing caused a switch to another
  thread.

> * uaccess_with_memcpy.c:__copy_to_user() has a mode in which it copies
>   "non-atomically" (if faulthandler_disabled() returns 0). If a fault
>   happens during __copy_to_user, what prevents some other thread from
>   clobbering DACR?

See the second point above.  Moreover, if we sleep in down_read(),
then __switch_to() reads the current DACR value and saves it in the
thread information, and will restore that value when resuming the
thread - even if the thread has been migrated to a different CPU.

> * In uaccess.h:uaccess_save_and_enable(), what prevents a context
>   switch between the get_domain and set_domain calls?

Nothing, but it doesn't matter, because the DACR register is saved
and restored to preserve its value across all exceptions and thread
switches.

I suspect the only way to nail this down is to litter the uaccess
code (virtually every alternate line) with:

	BUG_ON(get_domain() & domain_mask(DOMAIN_USER) ==
	       domain_val(DOMAIN_USER, DOMAIN_NOACCESS));

to narrow down the exact point where the domain register seemingly
gets reset.  Maybe it'll provide some hint.

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