[PATCH RFC 5/7] arm64: dts: Add power-controller device bindings for QCOM 8916 SoC

[Lina Iyer]

CPUs on the MSM8916 SoC has a power controller for each cpu that aids in
regualting power during active and idle usecase. Add SAW device bindings
for each cpu and L2.

Signed-off-by: Lina Iyer <lina.iyer at linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index ac4b3e5..a3232be 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -51,6 +51,7 @@
 			enable-method = "qcom,arm-cortex-acc";
 			qcom,acc = <&acc0>;
 			next-level-cache = <&L2_0>;
+			qcom,saw = <&saw0>;
 			L2_0: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
@@ -65,6 +66,7 @@
 			enable-method = "qcom,arm-cortex-acc";
 			qcom,acc = <&acc1>;
 			next-level-cache = <&L2_0>;
+			qcom,saw = <&saw1>;
 		};
 
 		CPU2: cpu at 2 {
@@ -74,6 +76,7 @@
 			enable-method = "qcom,arm-cortex-acc";
 			qcom,acc = <&acc2>;
 			next-level-cache = <&L2_0>;
+			qcom,saw = <&saw2>;
 		};
 
 		CPU3: cpu at 3 {
@@ -83,6 +86,7 @@
 			enable-method = "qcom,arm-cortex-acc";
 			qcom,acc = <&acc3>;
 			next-level-cache = <&L2_0>;
+			qcom,saw = <&saw3>;
 		};
 	};
 
@@ -254,5 +258,25 @@
 			reg = <0x0b0b8000 0x1000>,
 			      <0x0b008000 0x1000>;
 		};
+
+		saw0: power-controller at B089000 {
+			compatible = "qcom,msm8916-saw2-v3.0-cpu";
+			reg = <0xB089000 0x1000>, <0xB009000 0x1000>;
+		};
+
+		saw1: power-controller at B099000 {
+			compatible = "qcom,msm8916-saw2-v3.0-cpu";
+			reg = <0xB099000 0x1000>, <0xB009000 0x1000>;
+		};
+
+		saw2: power-controller at B0A9000 {
+			compatible = "qcom,msm8916-saw2-v3.0-cpu";
+			reg = <0xB0A9000 0x1000>, <0xB009000 0x1000>;
+		};
+
+		saw3: power-controller at B0B9000 {
+			compatible = "qcom,msm8916-saw2-v3.0-cpu";
+			reg = <0xB0B9000 0x1000>, <0xB009000 0x1000>;
+		};
 	};
 };
-- 
2.1.0