[PATCH v2] ARM: zImage: add support for ARMv7-M
Joachim Eastwood
manabian at gmail.com
Fri Sep 19 10:22:47 PDT 2014
This patch makes it possible to enter zImage in Thumb mode for ARMv7M
(Cortex-M) CPUs that does not support ARM mode. The kernel entry is
also made in Thumb mode.
Signed-off-by: Joachim Eastwood <manabian at gmail.com>
---
Hi,
Updated version of the patch which introduce AR_CLASS/M_CLASS macros
as suggested by Catalin. This reduces the amount of ifdefs needed in
compressed/head.S.
Successfully tested on NXP LPC4357 (Cortex-M4).
regards,
Joachim Eastwood
arch/arm/boot/compressed/head.S | 18 ++++++++++++++----
arch/arm/include/asm/unified.h | 8 ++++++++
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 413fd94b5301..75edba37bc04 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -11,7 +11,9 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
- .arch armv7-a
+ AR_CLASS( .arch armv7-a)
+ M_CLASS( .arch armv7-m)
+
/*
* Debugging stuff
*
@@ -114,7 +116,7 @@
* sort out different calling conventions
*/
.align
- .arm @ Always enter in ARM state
+ AR_CLASS( .arm ) @ Always enter in ARM state for AR class
start:
.type start,#function
.rept 7
@@ -133,6 +135,7 @@ start:
THUMB( .thumb )
1:
ARM_BE8( setend be ) @ go BE8 if compiled for BE8
+#ifndef CONFIG_CPU_V7M
mrs r9, cpsr
#ifdef CONFIG_ARM_VIRT_EXT
bl __hyp_stub_install @ get into SVC mode, reversibly
@@ -155,6 +158,7 @@ not_angel:
safe_svcmode_maskall r0
msr spsr_cxsf, r9 @ Save the CPU boot mode in
@ SPSR
+#endif
/*
* Note that some cache flushing and other stuff may
* be needed here - is there an Angel SWI call for this?
@@ -790,6 +794,9 @@ __common_mmu_cache_on:
call_cache_fn: adr r12, proc_types
#ifdef CONFIG_CPU_CP15
mrc p15, 0, r9, c0, c0 @ get processor ID
+#elif defined(CONFIG_CPU_V7M)
+ ldr r9, =0xe000ed00 @ CPUID register address
+ ldr r9, [r9]
#else
ldr r9, =CONFIG_PROCESSOR_ID
#endif
@@ -945,11 +952,13 @@ proc_types:
W(b) __armv4_mmu_cache_off
W(b) __armv6_mmu_cache_flush
+#ifndef CONFIG_CPU_V7M
.word 0x000f0000 @ new CPU Id
.word 0x000f0000
W(b) __armv7_mmu_cache_on
W(b) __armv7_mmu_cache_off
W(b) __armv7_mmu_cache_flush
+#endif
.word 0 @ unrecognised type
.word 0
@@ -1277,8 +1286,9 @@ __hyp_reentry_vectors:
__enter_kernel:
mov r0, #0 @ must be 0
- ARM( mov pc, r4 ) @ call kernel
- THUMB( bx r4 ) @ entry point is always ARM
+ ARM( mov pc, r4 ) @ call kernel
+ M_CLASS( add r4, r4, #1 ) @ enter in Thumb mode for M class
+ THUMB( bx r4 ) @ entry point is always ARM for AR class
reloc_code_end:
diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h
index b88beaba6b4a..200f9a7cd623 100644
--- a/arch/arm/include/asm/unified.h
+++ b/arch/arm/include/asm/unified.h
@@ -24,6 +24,14 @@
.syntax unified
#endif
+#ifdef CONFIG_CPU_V7M
+#define AR_CLASS(x...)
+#define M_CLASS(x...) x
+#else
+#define AR_CLASS(x...) x
+#define M_CLASS(x...)
+#endif
+
#ifdef CONFIG_THUMB2_KERNEL
#if __GNUC__ < 4
--
1.8.0
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