[PATCH v2] ARM: l2c: parse cache properties from ePAPR definitions

[Arnd Bergmann]

On Tuesday 09 September 2014 09:42:18 Arnd Bergmann wrote:
> > +     switch (set_size >> 10) {
> > +     case 512:
> > +             set_size_bits = 6;
> > +             break;
> > +     case 256:
> > +             set_size_bits = 5;
> > +             break;
> > +     case 128:
> > +             set_size_bits = 4;
> > +             break;
> > +     case 64:
> > +             set_size_bits = 3;
> > +             break;
> > +     case 32:
> > +             set_size_bits = 2;
> > +             break;
> > +     case 16:
> > +             set_size_bits = 1;
> > +             break;
> > +     default:
> > +             pr_err("L2C OF: cache way size: %d KB is not mapped\n",
> > +                    way_size);
> > +             break;
> > +     }
> > +
> > +     /*
> > +      * The l2x0 TRMs call this size "way size" but that is incorrect:
> > +      * the thing being configured in these register bits is actually
> > +      * the cache set size, so the variable here has the right name
> > +      * but the register bit definitions following the TRM are not
> > +      * in archaic naming.
> > +      */
> 
> No, I think actually the comment and the variable name are wrong here,
> and the TRM is right. I'm surprised you get the right results out of
> this. The set_size should be a relatively small number, e.g. 256 bytes
> in case of an 8-way associative cache with 32 byte lines. What is the
> pr_debug output and the properties you pass in for your example system?
> 

I just saw you had 'cache-sets = <8>' in your original DT file. That
is the wrong number, it needs to be 'cache-sets = <512>'. When you
fix that, you should get the right way_size as well.

	Arnd