[PATCH 5/7 v6] ARM: l2c: parse 'cache-size' and 'cache-sets' properties

Linus Walleij linus.walleij at linaro.org
Tue Sep 9 00:14:13 PDT 2014

On Mon, Sep 8, 2014 at 3:16 PM, Arnd Bergmann <arnd at arndb.de> wrote:
> [Me]
>> I can add a comment explaining that ARMs terminology does
>> not match the academic terminology or something, and say that
>> the thing we poke into "way-size" is actually "set size", if we agree
>> that is what we're seeing here.
> Let's see again: 16KB way-size * 8 ways = 128KB, that seems correct.
> 16KB way-size / 32B line-size = 512 sets, that also seems realistic.
> 128KB cache-size / 512 sets = 256B set-size. 256B / 32B = 8 ways,
> so everything fits together.

I've sent a v2 version of the patch using the terminology and calculations
from this thread, and it yields the right numbers, for PB1176, I will check
with the values from other RealView platforms to see if they also give the
same result back.

I had to squash Florians & my patch, it didn't make sense to have them
artificially separate.

Linus Walleij

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